The present invention generally relates to integrated circuit (IC) design and, more particularly, to clock and buffer tree synthesis, and balancing rising and falling edges of a signal during clock and buffer tree synthesis.
The design of electronic circuits is becoming increasingly complex due to shrinking sizes and increasing speeds. One design requirement is timing closure. Timing closure is a process in which a circuit design is modified to meet the timing requirements. Timing closure is achieved by balancing the rising and falling edges of signals in the circuit design at various stages of the circuit design process, such as clock tree synthesis, buffer tree synthesis, and timing optimization. Clock and data signals are balanced in these three stages to remove skew and latency.
Clock and data signals are balanced by optimizing signal paths using electronic design automation (EDA) tools. However, currently available EDA tools work effectively only in optimizing signal paths for the triggering edge of the signals, leaving the other edge unbalanced. Unfortunately, today's complex circuits sometimes now operate using both signal edges. Examples of circuits that use both edges of signals are double data rate (DDR) memory interfaces, latch based designs, and DDR debug interfaces. The differences in the characteristics of NMOS and PMOS devices results in asymmetry in delays in rising and falling edges in these circuit designs, and these differences need to be addressed separately because of the asymmetry. Thus, optimizing circuit designs only for the triggering edge of the signals offers limited results, especially in cases when the designs operate on both edges of the signals.
A few examples of circuit designs where balancing both edges of signals is important are shown in FIGS. 1-4. FIG. 1 is a schematic block diagram of a circuit design 100 that includes clock paths to an external double data rate (DDR) interface port 102. The circuit design 100 includes a clock driver 104 that supplies a clock signal to drive combinational logic 106. The output of the circuit design 100 is provided at the external DDR interface port 102. Both rising and falling edges of the clock signal need to be balanced because the DDR interface port 102 provides an output on both edges of the clock signal. If clock paths are optimized to balance only one edge, the skew at the other edge becomes inherent to the output.
FIG. 2 is a schematic block diagram of a circuit design 200 includes a clock source 202, a clock driver 204, combinational logic 206, output port 208 and sequential elements 210 and 212. The clock driver 204 supplies a clock signal to the combinational logic 206 and the combinational logic 206 outputs the clock signal to the output port 208, where it then is provide to the sequential elements 210, 212. Thus, the output port 208 acts as the clock source for the sequential elements 210 and 212. In this example, the sequential elements 210 are positive edge triggered and the sequential elements 212 are negative edge triggered. Thus, if the clock signal supplied by the output port 208 is not balanced for both the edges, there will be an inherent skew in the clock paths between the sequential elements 210 and 212.
FIG. 3 is a schematic block diagram of a circuit design 300 that includes a hard block 302. The hard block 302 includes a block port 304, positive edge triggered sequential elements 306, negative edge triggered sequential elements 308, and combinational logic 310. A clock driver 212 generates a clock signal that is provided to some external combinational logic 314 and the external combinational logic provides the clock signal to the block port 304. The block port then acts as a clock source for the sequential elements 306 and 308. If the clock signal at the block port 304 is not balanced for both edges, it will include an inherent skew for the clock paths between sequential the elements 306 and 308.
FIG. 4 is a schematic block diagram of a circuit design 400 that includes multiple external interface ports 410-416. The circuit design 400 includes data drivers 402 and 404 that provide data signals to corresponding combinational logic blocks 406 and 408, which in turn generate data signals that are available as output at the external interface ports 410-416. The data paths to the external interface ports 410-416 need to be optimized for latency and skew at the rising and falling edges to avoid timing and signal integrity (SI) violations.
FIG. 5 is a timing diagram representing an asymmetry in delays in rising and falling edges of a clock signal for the circuit design 300 of FIG. 3. The time period of the clock signal generated by the clock driver 312 is represented by Tp. The high period, i.e., the time period from a rising edge to the next falling edge is represented by Tr and the low period, i.e., the time period from a falling edge to the next rising edge is represented by Tf. For an ideal clock signal, Tr and Tf are equal. The clock signal received at the block port 304 includes asymmetric delays in the rising and falling edges due to non-optimized signal paths. As shown, the difference in delays in the rising and falling edges is delta (∂), which decreases the high period to (Tr−∂) and increase the low period to (Tf+∂). As a result, the time period available for the timing path between sequential elements 306 and 308 is reduced from Tr to (Tr−∂). Hence, the clock path needs to be modified or optimized so that the value of ∂ remains low, ideally zero.
Balancing both edges of the clock signal is crucial for the performance of a circuit design. As previously discussed, currently there is no optimal solution available for circuit designers to balance both edges. Designers often have to manually balance one edge using symmetric repeaters and symmetric combinational elements. This approach is difficult for many reasons. Firstly, this approach exacerbates asymmetry between the delay of rising and falling edges due to an increase in path lengths and numbers of combinational logic elements in the path. Secondly, manual balancing consumes a lot of time and requires multiple iterations. Thirdly, the results of manual balancing often result in poor quality of results (QoR).
Therefore, there is a need for a solution to balance the rising and falling edges of signals in circuit designs and to overcome the above-mentioned limitations of current EDA tools.